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MN195007
Hardware Specifications
Ver.1.0 2003/01/01
Panasonic Communications Co., Ltd.
Information found in this document, including specifications of the products described therein, is subject to change without notice.
This document presents hardware specifications of the MN195007. For information about the middleware that can be installed and its interfaces, refer to the relevant interface specifications.
- Contents 1. OVERVIEW .................................................................................................................... 3 .................................................................................................................... ................................................................
1.1 OVERVIEW................................................................................................................... 3 ................................................................................................................... ................................................................................................ 1.2 FEATURES .................................................................................................................... 3 .................................................................................................................... ................................................................
2. PIN ................................................................................................................................... 5 ................................................................................................................................ ...................................................................................................
2.1 PIN LAYOUT ................................................................................................................ 5 ................................................................................................................ ................................................................ 2.2 PIN LIST...................................................................................................................... 6 ...................................................................................................................... ................................................................................................ 2.3 PIN DEFINITIONS ....................................................................................................... 9 ....................................................................................................... ................................................................
3. ELECTRIC CHARACTERISTICS ........................................................................... 16 ................................................................ ...........................................
3.1 ABSOLUTE MAXIMUM RATING SPECIFICATIONS...................................................... 16 ...................................................... ................................ 3.2 RECOMMENDED OPERATION CONDITIONS ............................................................... 16 ............................................................... 3.3 INPUT / OUTPUT CAPACITY ...................................................................................... 17 ................................................................ ...................................................... 3.4 DC CHARACTERISTICS .............................................................................................. 17 ................................................................ ..............................................................
4. POWER CONSUMPTION CONTROL .................................................................. 20 ................................................................ .................................. 5. SERIAL INTERFACE SECTION ............................................................................ 21 ................................................................ ............................................
5.1 TYPE 3 SERIAL OPERATION ...................................................................................... 21 ................................................................ ...................................................... 5.2 OPERATABLE FUNCTIONS .......................................................................................... 22 ................................................................ .......................................................... 5.3 USAGE FOR TYPE 3 SERIAL MODE ............................................................................ 22 ................................................................ ............................................
6. FUNCTION EXPLANATION IN EACH MODE .................................................. 23 ..................................................
6.1 DSP MODE ................................................................................................................ 23 ................................................................................................................ ................................................................ 6.2 SERIAL INTERFACE MODE ......................................................................................... 26 ................................................................ ......................................................... 6.3 PARALLEL INTERFACE MODE ..................................................................................... 27 ................................................................ .....................................................
6. PACKAGE DIMENSION .......................................................................................... 30 ................................................................ ..........................................................
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MN195007 Hardware Specifications
1. Overview
1.1 Overview
The MN195007 is a 16-bit fixed-point DSP that implements high-speed signal processing. A DSP core, program memory, and work memory assembled on-chip can be combined with an analog front end (AFE) device to build a modem. The MN195007 is integrated 1 chip Digital Signal Processing LSI for FAX modem, Data modem and Voice control and it is suitable as a built-in modem solution. The V.34 FAX and Voice modem LSI MN195006 is the similar pin layout with the MN195007, so the MN195006 can be replaceable to the MN195007 with minor design change.
1.2 Features
(1) General Machine cycle 15.26 ns Standard input clock frequency 24.576MHz Internal operation clock frequency 65.536MHz Operable from a single +3.3V power supply Internal logic +1.8V operation (The internal regulator generates+1.8V.) 100-pin QFP package (0.5mm pitch, 14mmx14mm) Low power consumption mode Program ROM 768KB Internal Data RAM 64KB Internal Operation Mode ( 3 Modes ) - DSP mode ( MN195006 compatible mode ) - Serial interface mode - Parallel interface mode (2) DSP core Parallel execution ( CPU bus memory access, internal dual memory access, pointer change and AND/OR operations executable in a single instruction cycle ) Hardware multi-loop function Eight data memory pointer registers (3) Host interface Physical interface: Dual Port RAM(DPRAM) 1k x 16-bit Logical interface: Type 3 interface registers (4) Dual-channel AFE interface Four different interface modes supported - 16-bit serial interface - 8-bit PCM (-Law and A-Law CODEC) - 4-bit ADPCM - Time-division multiplex serial bus (IOM2
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MN195007 Hardware Specifications
(5) Key features of each operation mode a) DSP mode Supplied various kind of middleware for modem and voice processing Operation FAX Modem DATA Modem Voice Processing Support features V.34, V.17, V.29, V.27ter, V.23 V.90, V.34, V.32bis, V.22bis Codec MPC, G.711, G.726 (16,24,32kbps) Digital Echo Canceller Voice multipath Signal detection
b) Serial Interface mode / Parallel Interface mode Realize AT command modem with 1 chip Item Operation Mode Applicable Line Network Operation Method Number of Line Dialing Method Communication Method Communication Speed Error Correction Data Compression Control Command System interface Data Transfer Speed Data Format Specifications Serial Interface Mode Parallel Interface Mode Public Service Telephone Line Recommended NCU : AA / MA / AM / MM 1 channel BP( DTMF ) / DP( 10pps,20pps ) Data modem : Full Duplex Method Fax modem : Half Duplex Method Data : V.22, V.22bis, V.32, V.32bis, V.34, V.90 Fax : V.27ter, V.29, V.17 MNP Class 2,3,4 / V.42 MNP Class 5 / V.42bis Data : AT command compatible Fax : EIA-578( Class1 ) Standard Serial Interface 16550 Compatible Interface 460,800bps ( max. ) ---------Automatic Configuration ---------Function
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MN195007 Hardware Specifications
2. Pin
2.1 Pin Layout
ABITCLK EYEDAT EYECLK
75 74 73
72 71 70
69 68 67 66
65 64 63
62 61 60
59 58 57
56 55 54
DP 76 SCTS 77 VDD3 78 STXD 79 VSS 80 AFERST 81 AFESEL0 82 AFESEL1 83 A00 84 A01 85 VDD2 86 A02 87 A03 88 VSS 89 A04/GPIO20 90 A05/GPIO21 91 VDD3 92 A06/GPIO22 93 A07/GPIO23 94 A08/GPIO24 95 A09/GPIO25 96 VDD2 97 A10/GPIO26 98 SRXD 99 A11/GPIO27 100 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VSS D14/GPIO16 D15/GPIO17 1 2 3 4 5 6
53 52 51 50 MODE1 49 MODE0 48 MINTEST 47 VSS 46 TEST1 45 TEST0 44 VDD3 43 CLKOUT 42 VDD2 41 NRESET 40 VSS 39 XI 38 XO 37 CLKON 36 RING 35 AVSS 34 AVDD 33 TMS 32 VSS 31 TCK 30 VDD3 29 TDI 28 TDO 27 DBGMOD 26 NDBGREQ
Panasonic MN195007 MN195007
JAPAN
D03 D04 RTS
D01 VSS D02
VSS D06 D07
D08/GPIO10 VDD3 D09/GPIO11
VSS D10/GPIO12 D11/GPIO13
D00 VDD3
D05
[ Figure 1 ] Pin Layout
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D12/GPIO14 VDD2 D13/GPIO15
IRQ
REGOU2 REGOU1 LON
BBITCLK VSS ATXD
VSS VDDREG VDDREG
VDD2 ARXD ASPCLK
BTXD VDD3 BRXD BSPCLK
NCS NRD NWR
NLB NUB VSS
MN195007 Hardware Specifications
2.2 Pin List
2.2.1 Unique Pins Signal Name XI XO CLKOUT CLKON LON TEST0 TEST1 MINTEST MODE1 Pin # 39 38 43 37 51 45 46 48 50 I/O I O O I I I I I I Functions X'tal in ( 24.576MHz ) X'tal out ( 24.576MHz ) 24.576MHz Output Clock ON/OFF control Internal regulator control Test terminal ( "L" during normal operation ) Pull-down resistor is integrated when MINTEST. Mode setting terminal MODE MODE 1 0 0 0 0 1 1 0 Reset Input Operation Mode DSP Parallel Serial Conditio n when reset -------------
---
MODE0 NRESET EYECLK EYEDAT ABITCLK ASPCLK ATXD ARXD BBITCLK BSPCLK BTXD BRXD NDBGREQ DBGMOD TMS TCK TDI TDO RING DP SRTS SRXD SCTS STXD AFERST AFESEL0 AFESEL1
49 41 57 58 59 60 63 61 65 66 69 67 26 27 33 31 29 28 36 76 9 99 77 79 81 82 83
I I O O B B O I B B O I I O I I I O I O I I O O O I I
----L L Z Z Z --Z Z Z ----L ------Z --H Z Z H H L -----
Eye Pattern monitor connect terminal A A A A B B B B channel AFE bit clock channel AFE Sample clock channel AFE transmit data channel AFE receive data channel AFE bit clock channel AFE Sample clock channel AFE transmit data channel AFE receive data
Terminal for ICE During normal operation; TMS, NDBGREQ is "H" TCK, TCI is "L" DBGMOD, TDO is "Open" Ring-pass input Dial calling pulse output Serial transmit request ( PC -> MN195007 ) Serial receive data ( PC -> MN195007 ) Serial transmit permission ( PC <- MN195007 ) Serial transmit data ( PC <- MN195007) AFE reset signal AFE type signal 0 AFE type signal 1
[ Table 1 ] Unique Pin List
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MN195007 Hardware Specifications
2.2.2 Common Pins Signal Name nUB nLB nWR nRD nCS nIRQ D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 Pin # DSP Mode Condition when reset Signal I/O 71 Z NUB I 72 Z NLB I 73 Z NWR I 74 Z NRD I 75 Z NCS I 1 Z NIRQ O 2 Z D00 B 4 Z D01 B 6 Z D02 B 7 Z D03 B 8 Z D04 B 10 Z D05 B 12 Z D06 B 13 Z D07 B 14 Z D08 B 16 Z D09 B 18 Z D10 B 19 Z D11 B 20 Z D12 B 22 Z D13 B 24 Z D14 B 25 Z D15 B 84 --A00 I 85 Z A01 I 87 Z A02 I 88 Z A03 I 90 Z A04 I 91 Z A05 I 93 Z A06 I 94 Z A07 I 95 Z A08 I 96 Z A09 I 98 Z A10 I 100 Z A11 I Serial Mode Signal H H H H H H Ci DTR DSR DCD L L L L GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 --L L L GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 I/O O O O O O O O I O O O O O O B B B B B B B B I O O O B B B B B B B B Parallel Mode Signal RXRDY TXRDY NWR NRD NCS IRQ D00 D01 D02 D03 D04 D05 D06 D07 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 A00 A01 A02 L GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 I/O O O I I I O B B B B B B B B B B B B B B B B I I I O B B B B B B B B
[ Table 2 ] Common Pin List
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MN195007 Hardware Specifications
2.2.3 Power / Ground Pins Signal Name VDD3 VDDREG REGOUT VDD2 VSS AVDD AVSS Functions +3.3V Power ( For I/O ) +3.3V Power ( For internal regulator ) Regulator Output ( +1.8V ) +1.8V Power ( For internal logic ) VSS for I/O, internal logic ( Common ) Analog Power ( 3.3V ) for PLL Analog Power ( VSS ) for PLL I/O I I O I I I I 54,55 52,53 21,42,62,86,97 5,11,17,23,32,40,47,56, 64,70,80,89 34 35 Pin # 3,15,30,44,68,78,92
[ Table 3 ] Power / Ground Pin List On each tables, I/O code indicates as follows; I: Input O: Output B: Bidirectional (Direction determined by setting) Z: High impedance
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MN195007 Hardware Specifications
2.3 Pin Definitions
2.3.1 Unique Pin a) XI, XO Connect a 24.576 MHz crystal resonator. Use a crystal resonator only with its frequency deviations not exceeding 50 x 10-6 (with aging and temperature changes included). When using a crystal oscillator, apply a signal to XI, leaving XO open. Duty ratio: 40% to 60% Frequency deviation: Not exceeding 50 x 10-6 (with aging and temperature changes included) b) CLKOUT Buffered output of the signal input from a quartz resonator or quartz oscillator. Use CLKOUT as an AFE clock. Output clock signal during reset. c) LON Test pin. Set "High" set on this pin during normal operations. d) CKON Oscillation operation control and internal PLL control pin when a quartz resonator oscillator is used. "High" starts oscillation, and "Low" stops oscillation. Keep "High" set on this pin during normal operations. e) MINTEST, TEST1, TEST2 Test pins Keep "Low" set on these pins during normal operations. f) Mode [1:0] Operation mode select pins Mode [1] 0 0 1 1 Mode [2] 0 1 0 1 Operation Mode DSP Mode Parallel i/f Mode Serial i/f Mode Not used ( inhibit )
[ Table 4 ] Operation Mode List g) NRESET Reset pin "Low" on NRESET enables a reset; "High" cancels the reset. On a reset, the internal clock shuts down, saving the current drain. A reset takes effect in a minimum "Low" period of 100 ns while the power input and the CLKON pin are stable. Internal circuitry stabilizes 50 ms after the reset is canceled, getting the modem operation started.
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MN195007 Hardware Specifications
h) EYECLK, EYEDAT Eye pattern monitor connection pins i) ABITCLK, BBITCLK ASPCLK, BSPCLK ATXD, BTXD ARXD, BRXD Serial data clocks Serial data synchronization signals Transmitted serial data (MN195007 => AFE direction Received serial data (MN195007 => AFE direction
These AFE interface pins are divided into two channels: A and B. The first letter (A or B) heading each signal name identifies the channel name. The pin direction switches according to the AFE type set by GPIO [4] and [5].
AFE Type STLC7550 slave mode STLC7550 master mode Digital interface Si3044 Free pin handling ABITCLK BBITCLK Input Input Input Input Pull-up ASPCLK BSPCLK Output Input Input Input Pull-up ATXD BTXD Output Output Output Output Pull-down ARXD BRXD Input Input Input Input Pull-up
[ Table 5 ] AFE Interface Signal Directions Note: If a pin is out of use, be sure to carry out free pin handling as specified in [ Table 5 ]. Because ATXD and BTXD enter a high-impedance state when the output pin is reset, be sure to pull them down to finalize the level. j) AFESEL[0], AFSEL[1] AFE type selection pins Set pins depend of connecting AFE type as shown in [ Table 6 ] AFESEL [0] 0 0 AFESEL [1] 0 1 AFE Type STLC7550 Slave Mode STLC7550 Master Mode RLC5T882 Master Mode RL5T884 Master Mode Digital i/f Mode Si3044 Master Mode and RL5T884 ) is only supported with master mode.
1 0 1 1 * Ricoh AFE IC ( RTL5T882
[ Table 6 ] AFE Type Bit Assignment
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MN195007 Hardware Specifications
k) DP Dialing pulse Output pin The default is a high (i.e.) When dialing "3"
ON Huck Condition
OFF Huck Condition Reset / Idol During Plus Calling PB Waiting
* Please refer "MMD-5005 Modem Type 3 interface D-Mode Specifications" for more details l) Ring Ringing pulse input pin for ring detection Apply a ringing signal at the +3.3V logic level. Calculates the period between rising or falling edges of an input pulse. * Please refer "MMD-5005 Modem Type 3 interface D-Mode Specifications" for more details m) AFERST AFE reset signal. Output "Low" signal during Reset ( NRESET signal is "Low" ) n) VDD3 +3.3V power pin Supply +3.3V from an external source. o) VDDREG Internal regulator (+1.8V output) power pin Supply +3.3V. p) VREGOUT1, REGOUT2 Internal regulator voltage (+1.8V output pins Have a capacitor rated at 4.7F or higher inserted between these pins and VSS to stabilize the regulator. Wire this pin to VDD2. q) VDD2 +1.8V power input pin. (Power supplied to internal logic operation from +1.8V) Wire VDD2 to REGOUT and have a capacitor inserted between VDD2 and VSS. r) VSS GND pin. There is no distinction between +3.3V power and +1.8V power VSSs. s) AVDD PLL block power pin Supply +3.3V. There is no need to distinguish AVDD from VDD3 and VDDREG.
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MN195007 Hardware Specifications
t) AVSS PLL block GND pin There is no need to distinguish AVSS from VSS u) SCTS, SRTS, STXD, SRXD Signal lines for standard serial interface. All pins are negative logic. Possible to use DSP mode and Serial mode. If these pins are not used or use parallel mode, please set as follows; SRXD, SRTS : Pull-up ( Possible to connect VDD ) STXD, SCTS : Open EIA-232-E asynchronous communication is possible to use these 4 lines. SCTS : Transmit acceptance information to DTE ( to DTE from MN195007 SRTS : Transmit request from DTE ( from DTE to MN195007 STXD : Transmit data to DTE ( to DTE from MN195007 SRXD : Receiving data from DTE ( from DTE to MN195007 v) NDBGREQ, DBGMOD, TMS, TCK, TDI, TDO Test pins Keep followings set on these pins during normal operations. NDBGREQ, TMS pins : TCK, TDI pins : DBGMOD, TDO pins : "High" "Low" "Open" ) ) ) )
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MN195007 Hardware Specifications
2.3.2 Common Pins 2.3.2.1 DSP Mode a) NUB, NLB Host CPU interface signals NUB indicates that the upper-order side of the data line is valid. NLB indicates that the lower-order side of the data line is valid. Valid only on write; active "Low". b) NWR Host CPU interface signal Write pulse Active "Low". c) NRD Host CPU interface signal Read pulse Active "Low". d) NCS Host CPU interface signal Chip Select Active "Low". e) NCQ Host CPU interface signal Interrupt output "Low" on this level interrupt indicates that the interrupt is enabled. A pull-up resistance is required. f) D [15:0] Host CPU interface signal Data I/O g) A [11:0] Host CPU interface signal Address Input
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MN195007 Hardware Specifications
2.3.2.2 Parallel Interface Mode Host interface by 8 bit data bus, communicate through UART ( Universal Asynchronous Receiver / Transmitter ) IC16550 common resistor. a) NWR Host CPU interface signal Write pulse Active "Low". b) NRD Host CPU interface signal Read pulse Active "Low". c) NCS Host CPU interface signal Chip Select Active "Low". d) IRQ Host CPU interface signal Interrupt output "Low" on this level interrupt indicates that the interrupt is enabled. A pull-up resistance is required. e) D[7:0] Host CPU interface signal Data input/Output f) A[2:0] Host CPU interface signal Address input g) RXRDY Become "Active" when receive the data Active "Low". h) TXRDY Become "Active" when no transmit data in internal buffer Active "Low".
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MN195007 Hardware Specifications
i) GPIP[10:17], GPIO[20:27] I/O port Pin functions are set by the kind of software that is installed and are not userprogrammable. Pin No. GPIO[20] Function SP0 Description Speaker Control Pins Output SP1 Mute 0 Min 0 Mid 1 Max 1 ----E2PROM Serial Clock IN E2PROM Chip Select IN E2PROM Serial Data IN E"PROM Serial Data OUT --[ Table 7 ] GPIO Port Assignment Note : In case not using these pins, keep "Ping handling" condition set on these pins as mentioned [ table 7 ] SP0, SP1, and DO pins are output pin but they become "high Impedance" condition during "RESET", so pull-down handling is required to set the proper level. Non using terminal is possible to connect VDD directly. Connectable E2PROM is "FM93C86A" produced by Firechild 2.3.2.3 Serial Interface Mode a) CI, DTR, DSR, DCD Signal lines for standard serial interface. All pins are negative logic. EIA-232-E asynchronous communication is possible to use these 4 lines other 4 specifically assigned pins "SCTS, SRTS, STXD, and SRXD". CI : Call signal detect information to DTE ( to DTE from DTR : Transmit acceptance information from DTE ( from DTE to DSR : Transmit acceptance information to DTE ( to DTE from DCD : Carrier detect information to DTE ( to DTE from b) GPIP[10:17], GPIO[20:27] I/O port Same function as Parallel Interface Mode. Please refer to [ Table 7 ] for mode details. together with MN195007 MN195007 MN195007 MN195007 ) ) ) ) I/O SP0 0 1 0 1 Out Pull-up individually whichever these pins are used or not Out In In In In In Out In Pull-up or connect VDD Using : Pull-up individually Not Using : Pull-up or connect VDD Pull-up individually whichever these pins are used or not Pull-up or connect VDD Pin Handling
[21] [22] [23] [24] [25] [26] [27] GPIO[10:17]
SP1 ----SK CS DI DO ---
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MN195007 Hardware Specifications
3. Electric Characteristics
3.1 Absolute Maximum Rating Specifications
Item External Power Voltage *1 Internal Power Voltage *1 Input Pin Voltage Output Pin Voltage Output Current ( TYPE-HL4) *2 Power input current Acceptable Power Loss Operation temperature Storage Temperature Symbol VDD VDDI VI VO IO IV PD Topr Tstg Rating Specification -0.3 ~ +4.6 -0.3 ~ +2.5 -0.3 ~ VDD + 0.3 ( Max.4.6 ) -0.3 ~ VDD + 0.3 ( Max.4.6 ) +/- 12 +/- 70 ( each pin ) 520 0 ~ 70 -55 ~ 150 VSS=0V Unit V V V V mA mA mW C C
[ Table 8 ] *1 : In case VDD or VDDI is not supplied ( OFF ), output may be unstable condition. There is no specified sequence for power ON or power OFF. We recommend to power on for both VDD and VDDI at same time. *2 : Name of TYPE-HL4 pins ; NIRQ, A[01:11], D[00:15], NLB, NUB, NCS, NRD, NWR, DP, SCTS, SRTS, SRXD, STXD, ATXD, BTXD, ASPCLK, BSPCLK, ABITCLK, BBITCLK, AFERST, AFESEL[0:1], CLKOUT, DBGMOD, TDO, EYECLK, EYEDAT, REGOUT[1:2] Note : Absolute Maximum Rating Specifications is limit values which do not exceed at any conditions ( it may cause the damage or become worse. ) This specification values does not guarantee the operation.
3.2 Recommended Operation Conditions
Item External Power Voltage Internal Power Voltage Environmental Temperature Input rising time Input falling time Oscillation Frequency Symbol Condition Permissible Range Min 3.14 1.71 0 0 0 24.576MHz X'ta VDD=3.3V Implemented Feedback resistor 24.576 *Note Standard 3.3 1.8 Max 3.46 1.89 70 100 100 Unit V V
VDD VDDI
Ta tr tf fOSC1
C
ns ns MHz pF
External recommended CXIN Capacity CXOUT
Note : Oscillation characteristic should be determined with X'tal Supplier.
[ Table 9 ]
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MN195007 Hardware Specifications
3.3 Input / Output Capacity
Item Input Pins Output Pins Input/Output Pins Symbol CIN COUT CIO Condition VDD = VDDI = VI = 0V F = 1MHz Ta = 25C Permissible Range Min Standard 7 7 7 Max 8 8 8 Unit pF pF pF
[ Table 10 ]
3.4 DC Characteristics
Measurement conditions : VDD = 3.14 ~ 3.46V, VDDI = 1.71 ~ 1.89V, VSS = 0.00V, fTEST = 66MHz, Ta = 0 ~ 70 degrees C
Item
Symbol
Condition VI ( Pull-up ) = OPEN VI ( Pull-down ) = OPEN VI(XI) = VDD (*1) Other input pins and Hi-z condition of input/output pins should apply VSS or VDD level. VI = VDD or VSS f = 66MHz VDD = 3.3V VDDI = 1.8V Release output VI = VDD or VSS f = 66MHz VDD = 3.3V VDDI = 1.8V Release output
Permissible Range Min Standard Max
Unit
Static Power Current
IDDS
2 (*2)
mA
Operation Power Current
IDDO
40
mA
Internal Power Operation Power Current IDDIO
100
mA
(*1) : Power supply for X'tal oscillator is used separate power supply for measuring IDDS. (*2) : Environmental temperature should be 25 C.
[ Table 11 ]
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MN195007 Hardware Specifications
Item Oscillation Circuit : XO Internal feedback Resistor
Symbol
Condition
Permissible Range Min Standard Max
Unit
Rf7
VI = VDD or VSS VDD = 3.3V
1
M
Input LVCMOS Level : A00, LON, TCK, TDI, TMS, ARXD, BRXD, MODE[0:1], CLKON, RING SRTS, SRXD, AFESEL[0:1], TEST0, TEST1, NRESET, NDBGREQ Input Voltage "High" Level Input Voltage "Low" Level Input Leakage current VIH VIL ILI VI = VDD or VSS VDD X 0.7 0 VDD VDD X 0.2 +/- 10 V V A
Input LVCMOS Level ( With Pull-down resistor ) : MINTEST Input Voltage "High" Level Input Voltage "Low" Level Pull-down Resistor Input Leakage current VIH VIL RIL ILI VI = VDD VI = VDD or VSS VDD X 0.7 0 10 30 VDD VDD X 0.3 90 +/- 10 V V K A
Input/Output LVCMOS Level : NIRQ, A[01:11], D[00:15], NLB, NUB, NCS, NRD, NWR, DP, SCTS, STXD, AFERST ATXD, BTXD, ASPCLK, BSPCLK, CLKOUT, DBGMOD, TDO, EYECLK, EYEDAT Input Voltage "High" Level Input Voltage "Low" Level Output Voltage "High" Level Output Voltage "Low" Level Output Leakage Current VIH VIL VOH VOL ILO IOH = -4.0mA VI = VDD or VSS IOL = 4.0mA VI = VDD or VSS VO = Hi-Z Condition VI = VDD or VSS VO = VDD or VSS VDD X 0.7 0 VDD X 0.8 VDD X 0.2 +/-10 VDD VDD X 0.3 V V V V A
[ Table 12-1 ]
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MN195007 Hardware Specifications
Item
Symbol
Condition
Permissible Range Min Standard Max
Unit
Input/Output LVCMOS Level ( with Summit ) : ABITCLKBBITCLK Input Voltage "High" Level Input Voltage "Low" Level Output Voltage "High" Level Output Voltage "Low" Level Output Leakage Current VIH VIL VOH VOL ILO IOH = -4.0mA VI = VDD or VSS IOL = 4.0mA VI = VDD or VSS VO = Hi-Z Condition VI = VDD or VSS VO = VDD or VSS VDD X 0.8 0 VDD X 0.8 VDD X 0.2 +/-10 VDD VDD X 0.2 V V V V A
[ Table 12-2 ]
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MN195007 Hardware Specifications
4. Power Consumption Control
The table below lists the methods available for controlling power consumption.
No. (A)
CLKON NRESET
pin L
pin L
Status
Power consumption due to internal logic leak current Power consumption due to (A) , oscillator circuit and PLL circuit Normal operation
Operable blocks All circuits shut down Quartz oscillator circuit functioning Internal PLL VCO oscillating ( PLL inoperable ) All circuits shut down
(B) (C)
H H
L H
[ Table 13 ] Power Consumption Control Power consumption increases in the order of (A) -> (B) -> (C). Internal PLL starts operation after reset of condition (C). When PLL becomes stable after recovering RESET, reboot the modem operation. A control timing chart is given in Figure 2.
NRESET
Concurrently, or delay CLKON
Concurrently, or delay NRESET ( Note )
CLKON
Note : In case Crystal Oscillator is used, there is no problem to release NRSET and CLKON concurrently. However, in case Crystal resonator is used, NRESET should be released after stabilizing the oscillation circuit, otherwise wrong operation may occur due to CLKOUT signal is not stabilized. ( Oscillation circuit may stabilize after several decades msec. Please confirm with parts supplier or actual unit ) [ Figure 2 ] Power Consumption Control Timing
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MN195007 Hardware Specifications
5. Serial Interface Section
Serial communication has been performed to Host CPU when DSP mode or Serial Mode has been selected. On DSP mode, 4 signal lines ( SRXD, STXD, SCTS and SRTS ) assigned for serial communication pins can be used to perform standard serial communication. Normally 9 signal lines is assigned for modem control, but proper FAX/DATA modem operation can be performed by using these 4 signal lines. On Serial mode, in addition to above 4 signal lines, other signal lines ( CI, DTR DRS, and DCD ) assigned for common communication pins can be used to perform EIA-232-E asynchronous communication. *More details explanations for Serial Mode, please refer "6.2 Serial Interface Mode". Main features for this "Serial Interface" are : a) Support automatic configuration such as Automatic Speed Recognition, Automatic Format Recognition. b) Support 2400bps ~ 460.8Kbps. ( 2400, 4800, 7200, 9600, 14.4K, 19.2K, 38.4K, 57.6K, 76.8K, 115.2K, 230.4K, 460.8K ) c) Implement 32K bytes FIFO for Transmitting/Receiving Data, so that automatic flow operation can be performed by FIFO condition. d) Support EIA-232-E driver/receiver, so that PC's serial port can be connected. The Serial communication of DSP Mode is shown following paragraphs
5.1 Type 3 Serial Operation
"Type3 Serial Operation" is performed Serial communication with DSP mode. To use this "Type3 Serial Operation", set the mode selection pins to "DSP mode" and perform the "Type3 Serial Boot Command" from Host CPU, so that serial communication is performed even in DSP mode. "Type3 Serial Operation" can be performed to switch "Type 3 command controlled FAX modem" and "AT command controlled DATA modem" without changing the hardware design. Refer [ Figure 3 ] for Block Diagram and [ Figure 4 ] for Operation Image
TYPE3 i/f
MN 195007 Host CPU
SRXD STXD SCTS SRTS Serial i/f
AFE
Line
[ Figure 3 ] "Type3 Serial Operation" Connection Block Diagram in DSP Mode
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MN195007 Hardware Specifications
TYPE3 FAX Modem Operation AT Command Data Modem Operation
TYPE3 FAX Modem Operation
[ Figure 4 ] Operation Image for "Type3 Serial Operation" in DSP mode
Type3 Serial Mode Activate Command
Activate Soft Reset Return to TYPE3 Modem Mode
5.2 Operatable Functions
Outline of operatable functions in each mode is mentioned in [ Table 14 ]. In DSP mode, Type 3 command control (*) is used for modem operation. During this period, serial interface is not operatable. Also, "Error correction" and "Data Compression" functions such as V.42/V.42bis, MNP is not supported in Data communication.
Operatable Functions DPRAM i/f Serial i/f FAX Communication Correction/Compression DATA Communication Control Command DSP Mode O x Type3 Command Control x ( Implement in Host CPU) x ( Implement in Host CPU) Serial Mode x O Class1 Control O AT Command Control Type3 Serial Class1 Control O AT Command Control
O: : : x:
Operatable Not support for DSR and DTR ( Limited with AT Command ) Possible for parameter setting Impossible [ Table 14 ] Operatable Functions in each mode
5.3 Usage for Type 3 Serial Mode
For FAX communication, the detail parameter setting is required and Type 3 command control is suitable to use. Also, for DATA communication, AT command control is popular to use. Therefore, it is the best suited for both FAX and DATA communication by connecting MN195007 to Host CPU with DSP mode and operating with Type 3 serial mode.
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6. Function Explanation in each Mode
6.1 DSP Mode
6.1.1 Dual Port Memory Brock Physical interface between Host CPU, is used 2Kbytes dual port memory ( DPRAM ) and both 16 and 8 bit access is available. 6.1.1.1 Access Timing Assess timing is mentioned in [ Figure 6 ] and [ Figure 7 ]. It is the common timing to access DPRAM and Type 3 interface register ( Refer to "6.1.2 Type 3 Interface Register" )
Symb ol Normal timing Min 30 0 30 0 30 0 30 0 20 3 3 40 20 3 100 3 20 100 100 100 100 5 5 Max
If NDPWR is delayed after NUB, NLB
Item DPA set-up DPA Hold DPD Set-up DPD Hold NDPCS Set-up NDPCS Hold NUB, NLB Set-up NUB, NLB Hold NDPCS Negation Period NDPWR Hold during NDPCS Negation NDPRD Hold during NDPCS Negation NDPWR Pulse Width NDPWR Negation Period NDPCS Hold during NDPWR Negation NDPRD Pulse Width NDPCS Hold during NDPRD Negation NDPRD Negation Period NDPRD Access Time DPA Access Time NDPCS Access Time NUB, NLB Access Time DPD Output Hold Time
Min 40 -10 40 -10 40 -10 40 -10 20 3 3 40 20 3 100 3 20
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSA tHA tSD tHD tSC tHC tSB tHB tNC tHWC tHRC tWW tNW tHCW tWR tHCW tNR tAR tAA tAC tAB tHRD
100 100 100 100
ns ns ns ns ns
[ Table 15 ] DPRAM Access Time
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6.1.1.1 Write Timing
tSA A[*] tSB NUB/NLB tNC NCS tNW NWR tHRC NRD tSD D[*] tHD tWW tHWC tHCR tSC tHC tHCW tHB tHA
[ Figure 5 ] Timing chart for Writing
6.1.1.3 Read Timing
tSA A[*] tSB NUB/NLB tNC NCS tHWC NWR tWR tHCW tSC tHC tHCR tHB tHA
tHRC
NRD tAR tAC [ Figure 6 ] Timing Chart for Reading tAB tHRD tAA D[*]
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6.1.2 Type 3 Interface register Type 3 interface register is a physical interface between Host CPU and modem program. These registers constructed with 15 lines of 8 bit register and are connected with odd addresses. Register map is mentioned in [ Table 16 ].
Address 000 | 7FF 800 802 804 806 808 80A 80C 80E 810 814 816 818 81A 81C 81E Register Name DPRAM Area RXDR TXDR CMDR1 CMDR2 STSR1 EGSL1 T3IRQ1EN T3IRQ1DET STSR2 T3IRQ2EN T3IRQ2DET STSR3 EGSL3 T3IRQ3EN T3IRQ3DET R/W --R R/W R/W R/W R R/W R/W R/W R R/W R R R/W R/W R/W Receive Data Register Transmit Data Register Command Register 1 Command Register 2 Status Register 1 Interrupt Edge Control Register for Status Register 1 Interrupt Control Register for Status Register 1 Interrupt Accept Register for Status Register 1 Status Register 2 Interrupt Control Register for Status Register 2 Interrupt Accept Register for Status Register 2 Status Register 3 Interrupt Edge Control Register for Status Register 3 Interrupt Control Register for Status Register 3 Interrupt Accept Register for Status Register 3 Description
[ Table 16 ] Type 3 interface Register Map
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6.2 Serial Interface Mode
The EIA-232-E asynchronous Serial Interface is supported to use 4 dedicated signal lines ( SRXD, STXD, SCTS and SRTS ) and 4 common signal lines ( CI, DTR DRS, and DCD ). The Box modem for connect with the Serial port of PC, can be created to connect with the EIA-232-E Driver/Receiver IC as shown in [ Figure 7 ]. Also, embedded serial modem can be created to connect with serial port of Host CPU as shown in [ Figure 8 ]. * Not supported for voice processing function [ Features ] a) Support automatic configuration such as Automatic Speed Recognition, Automatic Format Recognition. b) Support 2400bps ~ 460.8Kbps. ( 2400, 4800, 7200, 9600, 14.4K, 19.2K, 38.4K, 57.6K, 76.8K, 115.2K, 230.4K, 460.8K ) c) Implement 32K bytes FIFO for Transmitting/Receiving Data, so that automatic flow operation can be performed by FIFO condition.
Box Modem
PC
EIA232E Driver/ Receiver
MN195007 Serial Mode AFE
COM
Line
[ Table 7 ] Box Modem Block Diagram
Embedded Modem
Host CPU
MN195007 Serial Mode AFE
Line
[ Table 8 ] Embedded Modem Block Diagram * Refer " MN195007 AT Command Specifications" for mode details of AT command.
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6.3 Parallel Interface Mode
MN195997 is implemented 16550A common register with is used as PC standard serial interface. Parallel Interface mode is bus connection interface by using these registers. The reference serial interface block diagram is shown in [ Figure 9 ]. The local bus of Host CPU is connected common asynchronous receiver/transmitter 16550A which is converted from parallel data to serial data, and connected to EIA232E Driver/receiver. MN195997 is connected via EIA232E Driver/Receiver and communicates to Host CPU with Serial communication. The interface point of MN195007 Serial mode is shown in [ Figure 9 ] a). For the connection of Parallel interface, interface point with Host CPU is shown in [ Figure 9 ] b) and connection diagram is shown in [ Figure 10 ]. Host CPU can be access directly to MN195007 16550 compatible register, so efficient AT command modem can be created without any speed limitation like as the serial interface. * Not supported for voice processing function
16550A
Host CPU Local Bus Host CPU
A[2:0] D[7:0] CS WR RD iRQ TXRDY RXRDY
EIA232E Driver/Receiver
EIA232E Driver/Receiver
DCD RXD TXD DTR DSR RTS CTS RI
+12V RS232C i/f
DCD RXD TXD DTR DSR RTS CTS CI
MN195007 AFE
Line
b) Interface Point for Parallel Mode
a) Interface Point for Serial Mode
[ Figure 9 CPU Host ] Serial Interface Block Diagram
Local Bus
A[2:0] D[7:0]
MN195007 Parallel Mode
Host CPU
CS WR RD iRQ TXRDY RXRDY
AFE
Line
[ Figure 10 ] Parallel Interface Block Diagram
Interface Point for Parallel Mode
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6.3.1 Access Timing Access timing is shown in [ Figure 11 ] and [ Figure 12 ]. 6.3.1.1 Write Timing
tSA A[*] tSC NCS tWW NWR tSD D[*] tHD tWWH tHC tWCH tHA
[ Figure 11 ] Timing Chart for Writing
.3.1.2 Read Timing
tSA A[ ] tSC NCS tWR NRD tAR tAC D[ ] tAA tHRD tWRH tHC tWCH tHA
[ Figure 12 ] Timing Chart for reading
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6.3.1.3 Operation Condition
Items Address Set-up Address Hold Chip Select Set-up Chip Select Hold H Level Period for Chip Select Data Set-up Data Hold Write Pulse Width Write H Level Period Read H Level period Address Access Chip Select Access Read Access Read Data Hold Symbol tSA tHA tSC tHC tWCH tSD tHD tWW tWWH tWRH tAA tAC tAR tHRD Min tSC + 5 or tWW + 5 5 35 0 20 35 0 35 20 20 ------2 Max --------------------tAC + 5 or tAR + 5 35 35 --Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
[ Table 17 ] DPRAM Access Time
6.3.1 Connection Reference MN195507 has operation experience PC Modem which used PC card interface IC.
+3.3V +3.3V
+5V - +3.3V
PC Card Connecter
Converter
A[2:0] D[7:0]
PCM16C02
CS WR RD iRQ TXRDY RXRDY
AFE
Line
PC Card MN195007 [ Figure 13 ] Parallel Mode Parallel Mode connection Diagram Controller
Panasonic Communications Co., Ltd.
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MN195007 Hardware Specifications
6. Package Dimension
[ Table 14 ] Package Dimensions
Panasonic Communications Co., Ltd.
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